The integrity requirements for personal computer systems has grown rapidly in the past few years. At the present time, newer operating systems and applications require a great deal of memory, and the amount of memory which can be accommodated in personal computer systems continues to increase rapidly. Such personal computer systems have in the past typically been provided only with the capability of writing and checking parity. In such a case, if a single bit of memory is corrupted, the non-parity condition will be flagged, and generally the system will halt when the error is detected. This poses a significant problem since users can ill afford to have periodic system crashes and/or loss of data, and as the amount of memory increases, the possibility of such data corruption increases significantly. Moreover, with the advent of large applications which normally require large amounts of memory, these are the most exposed to such crash and data corruption.
As indicated above, until very recently most conventional current low end personal computer systems contained only parity SIMMs which can detect single bit errors, but cannot correct such errors. Moreover, a parity function may not detect double or other multiple-bit errors.
One solution which has been proposed to eliminate system crash or loss of data due to single-bit errors is to provide error correction code for use in computer systems which do not have error correction code capabilities internal thereto. Typically, this error correction code allows for the detection of most double-bit errors and the correction of all single-bit errors. These schemes are a significant improvement over purely parity SIMMs. One technique for utilizing ECC is the so-called 32/7-bit ECC algorithm. This ECC algorithm requires 7 check bits for each double word (i.e., 4 bytes or 32 bits). This results in a 39-bit wide memory SIMM required for each double word and associated 7-check bits (32 data bits+7 check bits). Thus, the widely-used 36-bit wide memory SIMM is not available to be used, although this is a conventional and popular size SIMM and is used with double words containing only parity bits which requires only 36 bits (32 data bits plus 4 parity bits). Thus, the ECC requires an increase of 8% to 9% in storage capacity above that required for a similar number of data words, using only parity rather than ECC. However, this 32/7 bit ECC algorithm does allow for double bit detection and single bit correction. Typically a 40-bit wide SIMM is used for 32/7 error correction code resulting in one unused bit (i.e., 40 minus 32 minus 7 equals 1). Examples of how this is implemented on certain types of SIMMs are shown in U.S. patent applications Ser. No. 08/154,193, filed Nov. 17, 1993, and entitled "Initialization Methodology for Computer System Having Error Correction Code on Add-On Cards for Writing Portions of Data Words" (Atty. Docket No. BC9-92-053); Ser. No. 08/154,192, filed Nov. 17, 1993, and entitled "Error Correction Code with Write Error Preservation for Add-On Memory" (Atty. Docket No. BC9-92-067); and U.S. Pat. No. 5,452,429 entitled "Error Correction Code on Add-On Cards for Writing Portions of Data Words". Another complication which arises from using a 32/7-bit ECC algorithm is encountered due to the fact that SIMMs are created from memory modules which typically are 4, 8, 9, 16 or 18-bits wide. Thus, the amount of memory required must be selected as multiples of these module sizes. This may require extra memory space to store differently configured memory, as will be described presently.
Another potential technique for providing ECC is by use of the 64/8-bit ECC algorithm. In this algorithm, 8 check bits are generated for each quad word (i.e., 8 bytes or 64 bits) of data in memory. This technique takes advantage of the fact that the 64/8-bit ECC algorithm is as efficient as the 32/4-bit parity technique in the amount of memory needed for storage; i.e., if two parity SIMM addresses are used, the result is 2.times.32/4 or 64/8. Thus, the heed for additional modules to store the same amount of data is eliminated. However, if implemented conventionally, this technique has the disadvantage that it requires a 72-bit data path to memory (i.e., 64 data bits+8 parity bits=72 bits) including either a 32-bit or a 64-bit system bus. For a high performance system with large memory capacity and advanced CPUs, this implementation works well. However, for low-cost solutions, this is not an alternative since most personal computers are configured with a 32-bit memory bus, and thus the implementation would require a second 32-bits of memory bus and more control chips which would add significantly to the cost of this system.
Thus, it is an object of the present invention to provide an improved ECC on SIMM which uses no more capacity than conventional parity SIMMs and which can be implemented on a 32-bit memory bus.